There exists a continuing need to improve semiconductor device performance and further scale semiconductor devices. A characteristic that limits scalability and device performance is electron and/or hole mobility (e.g., also referred to as channel mobility) throughout the channel region of transistors. As devices continue to shrink in size, the channel region also continues to shrink in size, which can limit channel mobility.
One technique that may improve scaling limits and device performance is to introduce strain into the channel region, which can improve electron and/or hole mobility. Different types of strain, including expansive strain, uniaxial tensile strain, and compressive strain, have been introduced into channel regions of various types of transistors in order to determine their effect on electron and/or hole mobility. For some devices, certain types of strain improve mobility whereas other types degrade mobility.
One process known and used to create strain within the channel region is to form a layer of strain inducing material over the gate structure. The strain inducing material may then be subjected to an annealing process to create the strain within the channel region. Unfortunately, it has been observed that the introduction of just one kind of strain into the channel region using such a strain-inducing layer is insufficient to support some of the next generation devices.
Accordingly, what is needed in the art is an improved method for manufacturing a semiconductor device that provides improved channel mobility and/or lowered source/drain resistance.